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Shenzhen URCL-49B Manual

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BIOS SETUP UTILITY
DRAM Timing Control
Select Screen
Select Item
+- Change Option
F1 General Help
F9 Load Defaults
F10 Save and Exit
ESC Exit
v02.54 (C) Copyright 1985-2003, American Megatrends, Inc.
OC Tweaker
Select Screen
Select Item
+- Change Option
F1 General Help
F9 Load Defaults
F10 Save and Exit
ESC Exit
DRAM tCL
[Auto]
6
6
6
15
44
6
4
3
4
DRAM tRCD
DRAM tRP
DRAM tRAS
DRAM tRFC
DRAM tWR
DRAM tWTR
DRAM tRRD
DRAM tRTP
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
DRAM tCL
Value
Min=5
Max=10
DRAM Timing Configuration
DRAM tCL
This controls the number of DRAM clocks for TCL. Min: 5. Max: 10. The
default value is [Auto].
DRAM tRCD
This controls the number of DRAM clocks for TRCD. Min: 3. Max: 10. The
default value is [Auto].
DRAM tRP
This controls the number of DRAM clocks for TRP. Min: 3. Max: 10. The
default value is [Auto].
DRAM tRAS
This controls the number of DRAM clocks for TRAS. Min: 9. Max: 24. The
default value is [Auto].
DRAM tRFC
This controls the number of DRAM clocks for TRFC. Min: 15. Max: 78. The
default value is [Auto].
DRAM tWR
This controls the number of DRAM clocks for TWR. Min: 3. Max: 15. The
default value is [Auto].
DRAM tWTR
This controls the number of DRAM clocks for TWTR. Min: 2. Max: 15. The
default value is [Auto].
DRAM tRRD
This controls the number of DRAM clocks for TRRD. Min: 2. Max: 15. The
default value is [Auto].
DRAM tRTP
This controls the number of DRAM clocks for TRTP. Min: 2. Max: 13. The
default value is [Auto].
… 32 …


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