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Belinea 101536(111514) Service Manual
-18-
04/25/2005
SWITCHING PERFORMANCE
Maximum Conversion Rate 165 MSPS
Minimum Conversion Rate 20 MSPS
HSYNC Input Frequency 15 200 kHz
PLL Clock Rate 20 162.5 MHz
PLL Jitter 500 ps p-p
Sampling Phase Tempco TBD ps/°C
DIGITAL INPUTS
Input Voltage, High (VIH) 2.5 V
Input Voltage, Low (VIL) 0.8 V
Input Current, High (IIH) -1.0 uA
Input Current, Low (IIL) 1.0 uA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) VDDP-0.1 V
Output Voltage, Low (VOL) 0.1 V
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 250 MHz
Channel to Channel Matching 0.5% Full-Scale
3.3V Supply Voltages VVDD_33 -0.3 3.6 V
2.5V Supply Voltages VVDD_25 -0.3 2.75 V
Input Voltage (5V tolerant inputs) VIN5Vtol -0.3 5.0 V
Input Voltage (non 5V tolerant inputs) VIN -0.3 VVDD_33 V
C. MTV312M64
The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface,
4-channel A/D converter, and a 64K-byte internal program Flash-ROM.
A “CMOS output pin” means it can sink and drive at least 4mA current. It is not recommended to use such
pin as input function.
A “open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as input or
output function and needs an external pull up resistor.
A “8051 standard pin is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drives
at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to maintain the pin at
high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device.
POWER CONFIGURATION
The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all
output pins can swing from 0~5V, input pins can accept 0~5V input range.
And ADC conversion range is 5V. However, X1 and X2 pins must be kept below 3.3V.
In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V, HSYNC,
VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And the ADC conversion
range is 3.3V.
D. INVERTER
In order to drive the CCFLs embedded in the panel module, there is a push-pull inverter to convert by the controller.
from input 12V up to hundreds of AC voltage output peak to peak.
The inverter is formed by symmetric in order to drive the separate lamp modules.
The input stage consists of a PWM controller, push-pull inverter, and switching MOSFET to convert DC input into AC
output.
The output stage consists of a tuning capacitor, transformer, and push-pull MOSFET pair to boost AC output up to
hundreds of voltage peak to peak.
And one resister is serial to lamp for output voltage feedback.
There are two signals which control the inverter come from system to turn on the inverter and control brightness.
Logic “low” level which send to I901 is turn on the inverter.
BRI signal control brightness by DC level which was integral from PWM signal.
E. AUDIO
(
This function is operated on the models which with audio function)
The TDA7496L is a stereo 2W+2W class AB
power amplifier assembled in the @ Powerdip
20


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